1. Field of the Invention
The invention relates generally to integrated circuit design and, more particularly, to a process for defining complementary metal oxide semiconductor (“CMOS”) transistors.
2. Description of the Related Art
Integrated circuits are typically produced according to a series of complex fabrication steps including deposition, masking, etching and doping steps. The complexity of the fabrication greatly increases the cost of the integrated circuits, and often results in relatively low manufacturing efficiency.
For example, for memory circuits or devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs) and ferroelectric (FE) memories, the fabrication of the CMOS logic around the periphery traditionally comprises a number of relatively time-consuming and expensive masking steps.
First, a mask is used to define the active areas of the transistors in the CMOS by shallow trench isolation (STI). According to some manufacturing methods, this same masking stage may be used to simultaneously define active areas in the array by STI. Next, a gate oxide is defined, typically in both the periphery and array. Using one mask for the n-channel metal oxide semiconductors (NMOS) and another mask for the p-channel metal oxide semiconductors (pMOS), the well, n-channel enhancement implants and polysilicon workfunction implants are defined in the next step.
The polysilicon for forming the gates in the CMOS may then be formed using another mask. The lightly doped drain (LDD) implant and Halo implant (or pocket implant, as it is sometimes referred to) may then be formed around the CMOS gates using one mask for the NMOS, one mask for the pMOS, and yet another mask for the array.
Spacers are then typically formed along the vertical sidewalls of gate electrodes of both the periphery and array. The source and drain regions for the transistors may then be doped using a mask for each of the nMOS and pMOS regions. Finally, a low k gap fill oxide is deposited along the top of the memory device, and the device undergoes rapid thermal processing (RTP) for dopant activation. The transistors and other circuit elements of the array and periphery are thereby defined, and lines may then be connected thereto according to other steps well known to those of skill in the art.
As is clear from the description above, a typical CMOS fabrication process necessitates the use of many masks, and is a complex, time-consuming process. An exemplary CMOS fabrication process flow as described above, for example, employs eight (8) masks from definition of field isolation until transistor source/drain doping for each of the NMOS and pMOS regions. There is a need, therefore, for a less complex manufacturing technique that would use fewer masks, and that would also have an improved yield in comparison to traditional techniques.